The invention relates to a process for forming planar single or multilevel thin film wiring for interconnection of semiconductor integrated circuit devices, and more particularly, to a process for forming filled planar wiring and plugged contact hole(s) in a passivated semiconductor substrate.
Since the discovery of the planar transistor which enabled all the terminals of the transistor elements to be exposed on the surface of the chip and allowed the terminals of a large number of transistors to be connected together by a single deposition process, there has been an inexorable advance in device integration. The device density increase has been brought about principally by lateral shrinkage of the device dimensions. For example, at present 256 K dynamic random access memories (DRAM) are being mass-produced incorporating 400,000 transistors on a chip and having a pattern linewidth of about 2 .mu.m. The degree of integration has been trebling every four years. This trend is expected to continue. The present projection is that 4M DRAMs with a 0.7 .mu.m linewidth will be a reality in 1988 and 100M DRAMs with linewidths of 0.25 .mu.m incorporating approximately 100,000,000 transistors on a single chip will be devloped by the end of the present century.
As device density increases, the nature of the thin film interconnection metallization or wiring, which is the medium for electrically connecting the device components of the individual circuits to provide the logic or memory function of a chip, becomes extremely important. The interconnection must have functionality, i.e., it must complete all the connections to achieve the function desired of the chip without deleteriously affecting the performance or speed thereof. In this context, wireability, capacitance and resistivity are primary considerations. The design of the width of and spacing between wiring lines be such as to accommodate the wiring in the available limited chip real estate. The capacitance between interconnection lines at the same wiring plane and between planes should be a minimum. This necessitates use of an insulator material having a low dielectric constant, minimizing the thickness of the lines in a given wiring plane and maximizing the thickness of the insulator between wiring planes. High resistivity of the interconnection lines leads to large voltage drops and, therefore, unacceptable from a circuit performance standpoint. Another requirement of the interconnection is that it be reliable. That is, the wiring should be free from electromigration, junction penetration, corrosion and, in the case of multilevel systems, interlevel breakdown problems. Yet another requirement of the interconnection is that it be easily manufacturable, meaning that the process and materials combination have a large processing window so that routine manufacturing gives an acceptable yield. In addition to good yield, the process-material set should guarantee that the final product is free of defects which lead to failure during use.
A conventional method of forming thin film interconnection metallization in a fine pattern is by the additive process known as the lift-off method. The basic lift-off method is described in U.S. Pat. No. 2,559,389. Improvements to this method have been made as described in U.S. Pat. Nos. 3,849,136 and 3,873,361, all of which patents are assigned to the present assignee. In this method, typically, a semiconductor device substrate is coated with an organic photoresist material having a pattern of openings in accordance with the desired metallization pattern. A conductive metal layer is deposited on the resulting structure. The photoresist is then stripped off using a wet chemical etchant thereby removing the metal layer over the photoresist while leaving a metal pattern in contact with the substrate surface.
An improvement to the above lift-off method is disclosed in U.S. Pat. No. 4,004,044 issued to Franco et al and assigned to the present assignee. In this method a dual layer of a photoresist and polydimethylsiloxane resin materials is deposited on the substrate. Using a second photoresist layer having openings therein as a mask formed over the resin material, the latter is sputter etched. Using the defined resin material as a mask the first photoresist is, in turn, sputter etched to expose the regions of the substrate and also produce overhangs of the openings in the resin layer which facilitates easy lift off. Metal is then deposited onto the substrate through the openings in the resin and first photoresist followed by lift-off of these mask materials.
U.S. Pat. No. 4,076,860 issued to Kuroda discloses a method of forming thicker wiring than obtained by the lift-off process. In this process, after forming a nonplanar conductor film by the lift-off process utilizing a first layer of photoresist, a second photoresist is applied filling the valleys in the metal layer. Using the second photoresist as an etch mask unwanted metal is removed. Upon removing all the remaining photoresist, a wiring structure projecting from the substrate surface is obtained.
Another prior art method of forming chip-level wiring is by a subtractive process known metal RIE (reactive ion etching). In this process, a blanket layer of metal is deposited on the semiconductor substrate. Then, using an RIE mask having a pattern of openings, which is of an inverse configuration to the desired wiring pattern, the metal layer is patterned by RIE.
Thus, both the above substrate and additive processes obtain a wiring structure which is nonplanar. To form a planarized structure, an insulator is then deposited followed by a polishing process to remove the insulator over the metal pattern. The above processes are not only cumbersome, but also the wiring formed by these methods is susceptible to breakage due to stresses induced during the polishing process. The resulting structure invariably tends to have an irregular or nonplanar surface due to the vagaries of the polishing process. As a result, the methods are unsuitable for high density wiring due to their dependence on lithographic definition of the photoresist or the RIE mask openings, as the case may be, and inherent limitations of conventional lithography and alignment tolerances.
Reference is made to "Metal Lift-Off Process with a Self-aligned Insulation Planarization" by A. J. Hoeg et al, IBM Technical Disclosure Bulletin, Vol. 24, No. 9, pp. 4839-4840, February 1982, which discloses a method of producing planarized metal wiring. In this process a metal strip is set into a wide aperture in a nitride layer and a repetitive series of fill-in steps is performed to build-up the gap that is produced on either side of the metal, in order to form a smooth surface.
Another article by G. T. Chiu et al in the IBM Technical Disclosure Bulletin, Vol. 25, No. 10, pp. 5309-5314, March 1983, shows dual-level metallization formed by using the results of the Hoeg et al process as a starting point.
U.S. Pat. No. 4,307,179 issued to Chang et al and assigned to the present assignee discloses a method for forming planar interconnection metallurgy in which a dual layer of an organic polymerized resin material and glass is formed on the substrate. By reactive ion etching grooves are made in the dual layer, followed by a conformal metal layer deposition and filling of the depressions in the metal by a photoresist. Planar photoresist is then applied, etched to expose the high spots of the metal layer and the etching continued down to the level of the glass.
U.S. Pat. No. 4,508,815 issued to Ackmann et al discloses a method of forming metallization embedded at different levels in a glass layer. After forming a thick glass layer having a partial aperture in correspondence with the intended contact region on a substrate, a photoresist having openings in correspondence with the partial aperture and the intended metal pattern is formed. Then, the partial opening is fully opened while simultaneously forming the grooves in the surface portion of the glass layer in accordance with the intended metal pattern. By lift-off, metallization is formed in the glass layer openings and grooves.
These prior art process which employ photoresist to permit deposition of the metal interconnection pattern selectively on the substrate, basically suffer from outgassing of the photoresist during the metal deposition step. This outgassing leads to corrosion of the metal pattern leading to electromigration, open failures and reliability degradation. Also, from a manufacturability standpoint, they tend to be too complex.